1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular relates to a driving method for word lines of an NAND type flash memory.
2. Description of the Related Art
As a storage device, flash memories can be widely used in electronic devices, such as digital cameras or smart phones. In satisfaction of the market demand, the flash memory must satisfy needs of: small scale, large capacity, high access speed, and low power consumption, etc.
A NAND type flash memory comprises a memory block array where a plurality of NAND strings are arranged in the row or column direction. The NAND string comprises a plurality of memory cells connected in series and two selecting transistors respectively connected to the two ends of the series connection of the memory cells.
Typically, when a memory is written with data, the P-well, drain, and source, of the memory cell substrate, are applied with 0V, and the control gate is applied with a high writing voltage (for example 20V). When a delete operation is performed, the control gate is applied with 0V, and the P-well is applied with a high voltage (for example 20V) to delete the data of at least one memory block. When a read operation is performed, the control gate of the selected memory cell is applied with 0V, and the control gates of the other memory cells are applied with a voltage Vread which is higher than the power voltage Vcc. Therefore, several voltages higher than the power voltage Vcc should be generated in the operation of the flash memory, and then applied to the memory cells via the word lines.
One of the methods to raise voltage is by using a charge pump. When a word line decoder is provided with the charge pump, the scale of the word line decoder will increase substantially because of capacitors. To solve this problem, Patent document 1 discloses a word line decoder which reduces its layout scale by removing a charge pump. The word line decoder can self boost the voltage level of a word line enable signal to enable a word line, and restrain the voltage level of the word line enable signal from lowering down.
In addition, when a charge pump is used to raise the voltage level of the program voltage Vpgm or Vread, threshold voltages of NMOS transistors increase because of body effect, and this results in difficulty to sufficiently raise voltages. The word line decoder disclosed in Patent document 2 is used to solve the above problem. The word line decoder disclosed in Patent document 2 applies voltages to the gate and the drain of a pass-transistor connected to the word line at different timings. Thus, self-boost of the pass-transistor is used to avoid the lowering down of operation voltages while reducing circuit scale.    [Patent document 1] Japan patent application publication 2002-197882    [Patent document 2] Japan patent application publication 2006-107701
However, there are still problems for the word line decoder of a conventional flash memory which are as follows. FIG. 1A shows a layout of the word line decoder of a conventional flash memory. In the row direction, one end of the memory array is arranged with a word line decoder, a level shifter (both of them are called as a word line decoder 20 thereafter), and a word line drive circuit 22. In the column direction, one end of the memory array is arranged with a page buffer 30. In this example, the memory array 10 is divided into 2 memory arrays. The word line decoder 20 provides the required operation voltages to a selected word line and unselected word lines according to an address signal. The operation voltages include a program voltage Vpgm, applied to the selected word line during a writing operation, a pass voltage, applied to the unselected word lines during the writing operation, a ground voltage, applied to the selected word line a during reading operation, and a reading voltage, applied to the unselected word line the during reading operation.
The word line drive circuit 22 comprises a pass transistor for transmitting an operation voltage from the word line decoder 20 to the gate of a memory cell. The operation voltage is applied to the memory cell by turning on the pass transistor. The word line drive circuit 22 applies a high voltage to the gate of the pass transistor to restrain the operation voltage from lowering down.
As shown in FIG. 1A, the word lines WL0, WL1 . . . WLn connected to the word line drive circuit 22 must be arranged across the memory array 10 in the row direction. The word line should be applied with a high program voltage Vpgm (for example, 20V) during a writing operation. If the resistance capacity (RC) of the word line increases, the voltage will take more time to arrive at the end of the word line. In addition, in order to provide the program voltage Vpgm to the memory cell at the end of the word line, a high program voltage Vpgm should be applied to the word line, and this increases power consumption substantially. Moreover, if the width of the word line is wide enough to reduce the wire resistance thereof, it is hard for the memory array to be minimized.
On the other hand, the pass transistor of the word line drive circuit 22 is constructed by an N-MOS transistor. To restrain from lowering down of the threshold value of the program voltage Vpgm, the gate of the pass transistor must be applied with a voltage higher than the program voltage Vpgm. Therefore, in order to raise the withstand voltage of the gate oxide layer, the thickness of gate oxide layer must be increased (for example, 400 Å), and this increases the size of the transistor and also the circuit area of the word line drive circuit 22. Furthermore, if the word line drive circuits 22 are arranged with a narrow pitch therebetween, latch-up will easily occur between adjacent pass transistors. In this regard, an appropriate pitch should be kept between the pass transistors, but such arrangement would increase the chip area.
FIG. 1B shows another layout of a conventional flash memory. In this example, word line decoders 20A and 20B and word line drive circuits 22A and 22B are arranged at the left end and the right end of the memory array. The word line decoders 20A and the word line drive circuit 22A work for the memory array 10A, and the word line decoders 20B and the word line drive circuit 22B work for the memory array 10B. The page buffer 30A below the memory arrays 10A and 10B performs data reading or writing for odd bit lines, and the page buffer 30B above the memory arrays 10A and 10B performs data reading or writing for even bit lines
As shown in FIG. 1B, though the wire lengths of the word lines WL0, WL1 . . . WLn in the row direction can be reduced to be a half of that shown in FIG. 1A, a word line decoder and a word line drive circuit should be arranged at both the two ends of the memory array, such that the chip area is increased.
The purpose of the invention is to solve the problem on the conventional art, and provide a semiconductor memory device capable of reducing the electric fields applied to the word lines on the memory arrays and also reducing the area of the chip including the memory arrays and the peripheral circuits.